Referring to FIG. 1, a conventional MOS transistor is generally designated by the reference numeral 10 and is seen to include a source region, drain region and a gate region. The gate region includes a polysilicon layer 1, a gate oxide layer 3 and an oxide spacer 5. The transistor 10 also includes a substrate 7 having source/drain diffusion regions 9 and lightly doped drain structures 11. A silicide layer 13 is formed on top of the polysilicon layer 1 and source/drain diffusion regions 9. A field oxide region 15 is located adjacent the source and drain regions.
The substrate 7 also includes a depletion region 17 and a region 19 where hot carrier injection induced damage can occur. This hot carrier injection problem can arise when the device dimensions are reduced but the supply voltage is maintained constant. This results in an increase in the electric field generated in the silicon. The intensified electric field can the make it possible for electrons in the channel of the transistor to gain sufficient energy to be injected into the gate oxide. The charging of the gate oxide causes a long term device degradation, which raises the threshold voltage of the device and reduces its transconductance.
One prior art approach to lower degradation from hot carrier injection induced damage is the use of the lightly doped drain regions 11. The disadvantage of lightly doped drain regions is that they raise the parasitic resistance from the source to the channel and, consequently, lower the current available and reduce the device speed.
The hot carrier injection typically occurs at the drain end of the transistor as shown in FIG. 1, reference numeral 19. Current and threshold voltage are determined mainly at the source/channel interface, i.e. the tip of the source/side LDD and in the inversion channel. Neither of these extends into the area depleted by the drain-body voltage.
The use of lightly doped drain regions to minimize hot carrier injection induced damage is becoming less effective at dimensions below 0.25 microns. Consequently, a need has developed to design an MOS transistor which overcomes the deficiencies noted above in prior art devices.
Ways to increase device speed can be addressed by considering the relationship between the capacitive load being switched, the voltage swing of the switch and device current. Device switching speed can be boosted by either raising current or lowering capacitance.
The present invention overcomes the disadvantages of prior art MOS transistors through the utilization of a void space which eliminates a portion of the gate oxide layer where carriers injected by hot carrier effects lodge. Thus, gate capacitance is lowered and device speed is increased.